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e application note ap-645 3 volt and 5 volt flashfile? memory mi g ration guide o r d er n um b er: 292203-003 december 1998 note: this document formerly known as word-wide flashfile? memory (28f160s3, 28f320s3, 28f160s5, 28f320s5) migration guide.
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-9808 or call 1-800-548-4725 or visit intels website at http://www.intel.com copyright ? intel corporation 1997, 1998 cg-041493 *third-party brands and names are the property of their respective owners.
e ap-645 3 contents page page 1.0 introduction............................................. 5 2.0 conversion checklist ........................... 5 3.0 hardware compatibility....................... 7 3.1 pinout .......................................................... 7 3.2 multiple voltage options .............................. 7 3.3 write protection using v pplk ....................... 8 4.0 software compatibility ....................... 8 4.1 common flash interface (cfi) .................... 8 4.2 scaleable command set (scs)................... 9 4.3 intel basic command set (bcs).................. 9 4.4 command superset..................................... 9 4.4.1 read query mode command ............. 10 4.4.2 enhanced intelligent identifier operation........................................... 10 4.4.3 enhanced suspend operations .......... 10 4.4.4 block locking and block status operations ......................................... 11 4.4.5 writing to the buffer ............................ 11 4.4.6 full chip erase ................................... 11 4.4.7 sts configuration............................... 11 4.4.8 commands not supported on the s3/s5................................................. 11 4.5 command queuing.................................... 12 4.6 status registers ........................................ 12 5.0 design for forward-compatibility 13 5.1 hardware................................................... 13 5.1.1 pinout ................................................. 13 5.1.2 v cc voltage ........................................ 14 5.1.3 v pp voltage......................................... 15 5.1.4 write protection via v pplk .................. 16 5.1.5 read/write performance..................... 16 5.2 software .................................................... 16 5.2.1 command set compatibility................ 16 5.2.2 software identification of 28f016sa, 28f016sv or 28f160s3/s5 ............... 16 6.0 conclusion .............................................. 16 appendix a: additional information............... 17 figures figure 1. bcs, scs, and cfi ........................... 8 figure 2. v cc jumper selection ...................... 15 figure 3. v pp jumper selection ...................... 15 tables table 1. hardware checklist for sa/sv migration to s3/s5............................... 6 table 2. software checklist for the sa/sv migration to the s3/s5 ......................... 7 table 3. 3 volt/5 volt flashfile? memory pinout differences ............................... 7 table 4. 28f160/320s5: voltage combinations 8 table 5. 28f160/320s3: voltage combinations 8 table 6. summary of command changes between the sa/sv and the s3/s5 ..... 9 table 7. identifier code comparison............... 10 table 8. sts and ry/by# configurations ...... 12 table 9. status register bit cross reference: sa/sv to s3/s5 ................................. 14 table 10. v cc voltage comparison ................ 15 table 11. v pp voltage comparison................. 15
ap-645 e 4 revision history date of revision version description 06/09/97 -001 original version 12/02/97 -002 updated all references to 28f160s3/s5 to include 28f320s3/s5. updated section 1.0 introduction to clarify descriptive text. updated section 3.1 pinout. added table 3 and adjusted all subsequent table numbers. corrected documentation error in table 5. added figure 1 and adjusted all subsequent figure numbers. corrected documentation error in table 7. updated section 4.4.3 enhanced suspend operations to clarify descriptive text. updated section 4.4.8 commands not supported on the s3/s5 to clarify descriptive text. removed section on specification differences. updated figure 2 and figure 3 and all associated references. updated section 6.0 conclusion to clarify descriptive text. moved rev -001 section 6.0 conversion checklist to section 2.0. updated rev -001 table 19 checklist , split it into two tables, and moved it to table 1 and table 2. adjusted all subsequent section numbers and table numbers. updated appendix a document references. 12/01/98 -003 name of document changed from word-wide flashfile? memory (28f160s3, 28f320s3, 28f160s5, 28f320s5) migration guide
e ap-645 5 1.0 introduction this application note discusses design migration from 28f016sa/sv flashfile ? memories to 3 volt and 5 volt flashfile memories (28f160s3, 28f320s3, 28f160s5, 28f320s5). the remainder of this application note will refer to 28f016sa/sv devices as sa/sv and 28f160s3, 28f320s3, 28f160s5, and 28f320s5 devices as s3/s5. the s3/s5 memory devices provide enhancements which reduce cost, increase performance and ease upgrades: multiple voltage options common flash interface (cfi) support scaleable command set (scs) support enhanced suspend operations two 32-byte buffers new status register structure in addition, s3/s5 are manufactured on intels 0.4 micron etox? v process technology. sa/sv are manufactured on intels 0.6 micron etox iv process technology. the intel 0.4 micron etox v process technology reduces manufacturing costs. this application note focuses on three topics: hardware compatibility software compatibility design for forward-compatibility the first two sections highlight specific differences between sa/sv and s3/s5. the last section will discuss how to design in a sa/sv device today for upgrade to a s3/s5 in the future. this documentation is meant for use with the 3 volt- flashfile? memory 28f160s3, 28f320s3 datasheet and/or 5 volt- flashfile? memory 28f160s5, 28f320s5 datasheets. please refer to the documentation listed in appendix a of this application note for a full description of all flash memory components discussed in this application note. 2.0 conversion checklist table 1 and table 2 provide a brief overview of the hardware and software changes required to migrate from sa/sv to s3/s5. table 1 is a checklist of hardware changes and table 2 is a checklist of software changes that need to be considered when converting to s3/s5 or when designing in an upgrade path to s3/s5.
ap-645 e 6 table 1. hardware checklist for sa/sv migration to s3/s5 migrating from sa/sv migrating to s3/s5 changes required refer to section three pinout differences: 3/5# ry/by# a 21 3/5# pin becomes nc ry/by# pin becomes sts a 21 pin on 32-mb device nc may be driven or floated be aware of operational differences between ry/by# and sts pins. sts in default mode is the same as ry/by in default mode connect a 21 on 32-mb device 3.1 uses 12 v v pp 12 v v pp not available for 28f160/320s3: connect v pp to 2.7 v, 3.3 v or 5 v (away from 12 v v pp ) for 28f160/320s5: connect v pp to 5 v (away from 12 v v pp ) 3.2 and 5.1.3 uses 3.3 v or 5 v v cc (2.7 v v cc is not available on the sa/sv) 2.7 v v cc is available on 28f160/320s3 connect v cc to 2.7 v if desired (away from 5 v is required or away from 3.3 v if desired) 3.2 and 5.1.2 uses 5 v or 12 v v pp (2.7 v and 3.3 v v pp is not available on sa/sv) 2.7 v and 3.3 v v pp is available on 28f160/320s3 connect v pp to 2.7 v or 3.3 v if desired (away from 12 v v pp is required or away from 5 v if desired) 3.2 and 5.1.3 28f016sa is write protected when v pp = v cc device is write protected when v pp v pplk , not when v pp =v cc provide a means to switch v pp to gnd 3.3 and 5.1.4 65 ns access time available on 28f160sv no 65 ns access time available on s3/s5 28f160s5 has 70 ns access time datasheet some dc and ac characteristics on the sa/sv change some dc and ac characteristics on the s3/s5 differ change design as necessary datasheet sa/sv are available in tsop and ssop packages. 28f160s3/s5 are available in tsop and ssop packages. 28f320s3/s5 are available in ssop packages. consider packages available datasheet
e ap-645 7 table 2. software checklist for the sa/sv migration to the s3/s5 migrating from sa/sv migrating to s3/s5 solution refer to section sa/sv use the 28f008sa compatible command set and performance- enhancement command set s3/s5 use the cfi-scs compatible command set create new software or update existing software for commands listed in table 6. use device identification method described in section 5.2.2. 4.1, 4.2, 4.3, 4.4 and 5.2 command queuing available on sa/sv no command queuing available on s3/s5 designs incorporating command queuing will need to update software by polling for wsm ready or create new software 4.5 status register bits arranged differently on sa/sv status register bits arranged differently on s3/s5 refer to table 9 to make sure correct bit is being polled in software 4.6 3.0 hardware compatibility 3.1 pinout there are three pinout differences between the s3/s5 and sa/sv memories. these difference are summarized in table 3. the 3/5# pin on the sa/sv, which is used to configure internal circuits for operation at either 3.3 v or 5 v v cc , has become a no connect (nc) pin on the s3/s5. the 28f160/320s3 operates at 2.7 v or 3.3 v v cc and the 28f160/320s5 operates at 5 v v cc . the no connect pin is not internally connected and may be driven or floated. second, the ry/by# pin on the sa/sv has become the sts pin on the s3/s5. both the ry/by# pin (on the sa/sv) and sts pin (on the s3/s5) operate in the same way at device power-up. they both default to a level- mode ry/by# configuration at device power-up. in this configuration, the device pulls the ry/by# or sts pin low whenever the write state machine (wsm) is busy performing an operation. both pins can be configured in software. see section 4.4.7 for further information. the last pinout difference is an extra address pin (a 21 ) on the 32-mbit device (28f320s3/s5). this pin is a no connect (nc) on the 16-mbit devices. table 3. 3 volt/5 volt flashfile? memory pinout differences migrating from sa/sv to 28f160s3/s5 to 28f320s3/s5 3/5# nc nc ry/by# sts sts nc nc a 21 note: the dc characteristics have changed somewhat between the devices. some pins may handle different voltages or currents on the s3/s5 than they did on the sa/sv. refer to the datasheets for further information. 3.2 multiple voltage options the s3/s5 devices incorporates both fast programming and low-power operation. this voltage flexibility allows designers to incorporate different voltage combinations in their applications. fast program and erase performance can be realized at 5 v v pp on both the 28f160/320s3 and 28f160/320s5. low-power operation occurs at 2.7 v or 3.3 v v pp on the 28f160/320s3 and 5 v v pp on the 28f160s3/s5 and 28f320s3/s5.
ap-645 e 8 table 4. 28f160/320s5: voltage combinations v cc voltage v pp voltage 5.0 v 5.0 v table 5. 28f160/320s3: voltage combinations v cc voltage v pp voltage 2.7 v 2.7 v, 3.3 v and 5.0 v 3.3 v 3.3 v and 5.0 v there is no 12 v v pp available on the s3/s5. applying 12 v v pp to the s3/s5 could damage the device. the s3/s5 provides faster programming at 5 v v pp than the sa/sv at 12 v v pp . 3.3 write protection using v pplk as a write protection method, some 28f016sa applications may pull v pp voltage to v cc when not in use. however, the s3/s5s v cc voltage is not low enough to lockout program and erase operations. on these devices, v pp should be pulled below v pplk to protect data. an external pulldown resistor can be used to pull v pp to gnd when not in use. other write protection alternatives like rp# and wp# should also be used. 4.0 software compatibility this application note is intended to give an operational overview of the differences between the sa/sv and the s3/s5 memory devices. for complete information on command sets, refer to the datasheets. figure 1 shows that the intel basic command set (bcs) is a subset of the intel scaleable command set (scs). 4.1 common flash interface (cfi) the s3/s5 supports cfi. this specification allows for compatibility between the s3/s5 and future cfi- compliant devices. by incorporating cfi, software can be standardized for long-term compatibility. for more information on cfi, refer to ap-646, common flash interface and command sets or the cfi specification. flash industr y cfi cfi extended command set vendor specific (intels scs) standard command set vendor specific (intels bcs) 2203_01 figure 1. bcs, scs, and cfi
e ap-645 9 4.2 scaleable command set (scs) the s3/s5s scs command definitions are similar in function to the performance-enhancement commands on the sa/sv. however, the command codes are different. software changes may be required to migrate from the sa/sv to the s3/s5 devices. for more information on scs, refer to ap-646, common flash interface and command sets . 4.3 intel basic command set (bcs) the intel bcs, formerly the 28f008sa compatible command set, is the same between the s3/s5 and the sa/sv. if your software makes use of only the commands contained in the intel bcs, minimal software updates are required. in this case, note that the intelligent identifier and suspend commands have been enhanced. see sections 4.4.2 and 4.4.3 for further information. 4.4 command superset commands summarized in table 6 show which commands on the s3/s5 have been enhanced, added, and deleted in comparison to the sa/sv. commands labeled enhanced on s3/s5 have the same command codes between the s3/s5 and the sa/sv, but have been improved in some way. commands labeled new on s3/s5 have new command codes that were not available on the sa/sv. some commands, labeled not supported on s3/s5 are replaced by new s3/s5 commands. commands not supported on s3/s5 and their new replacement commands have been grouped in the table. other unsupported commands are not replaced by any s3/s5 command. commands not listed in table 6 operate exactly the same between the devices. table 6. summary of command changes between the sa/sv and the s3/s5 command function command code enhanced on s3/s5 new on s3/s5 not supported on s3/s5 notes intelligent identifier 90h 4 suspend b0h 4 lock block / confirm 77h/d0h 4 set block lock-bit / confirm 60h/01h 4 clear block lock-bits / confirm 60h/d0h 4 2 single load to page buffer 74h 4 sequential load to page buffer e0h 4 page buffer write to flash 0ch 4 write to buffer / confirm e8h/d0h 4 erase all unlocked blocks / confirm a7h/d0h 4 full chip erase / confirm 30h/d0h 4 device configuration 96h/cc 4 3 sts configuration b8h/cc 4 3
ap-645 e 10 table 6. summary of command changes between the sa/sv and the s3/s5 (continued) command function command code enhanced on s3/s5 new on s3/s5 not supported on s3/s5 notes read query 98h 4 read extended status register 71h 4 1 read page buffer 75h 4 page buffer swap 72h 4 two-byte program fbh 4 upload status bits 97h 4 upload device information 99h 4 sleep f0h 4 abort 80h 4 notes: 1. the status registers differ between the sa/sv and the s3/s5. please see section 4.6 for more information. 2. the sa/sv parts unlock blocks by performing an erase on a locked block with wp# at logic high. 3. cc = configuration code. see section 4.4.7 for more information. 4.4.1 read query mode command the read query command (98h) allows reading of the common flash interface (cfi) query structure. the cfi specification allows for future compatibility. system software should parse this structure to gain critical information about flash writes, block erases, and other flash component characteristics. the query is part of an overall specification for multiple command set and control interface descriptions called common flash interface, or cfi. for more information on cfi and its use in this device see the datasheets, application note ap-646 , common flash interface and command sets , or the cfi specification. 4.4.2 enhanced intelligent identifier operation the intelligent identifier command (90h) has been renamed the read identifier codes command (90h) on the s3/s5. it continues to output the manufacturer code and device code. in addition, it has been enhanced to supply each blocks lock configuration code. see the s3/s5 datasheets for the device identifier memory map. the manufacturer and device identifier codes are different between the sa/sv and the s3/s5. table 7 compares identifier codes. for the complete identifier codes description for the s3/s5, see the datasheets. table 7. identifier code comparison device manufacturer code device code 28f016sa 89h a0h 28f016sv 89h a0h 28f160s3/s5 b0h d0h 28f320s3/s5 b0h d4h 4.4.3 enhanced suspend operations the sa/sv supports the erase suspend to read command (b0h). the s3/s5 enhances the following suspend capabilities: erase suspend to read erase suspend to program program suspend to read the erase suspend command (b0h) interrupts a block erase so that another block can be read or programmed. status register bit sr.6 reflects the erase suspend status. any programming operation that is initiated during a suspended block erase can be suspended using the program suspend command.
e ap-645 11 the program suspend command (b0h) suspends byte/word programming as well as buffered programming so that another byte/word can be read. status register bit sr.2 reflects the program suspend status. refer to section 4.6 for more status register information. all three suspend operations are continued by issuing the resume command (d0h), the same as on the sa/sv. note that a block erase cannot resume until program operations initiated during block erase suspend have completed. 4.4.4 block locking and block status operations the block locking capability of the s3/s5 is similar to that of the sa/sv. the blocks are individually locked using a combination of hardware and software. like the sa/sv, a block lock-bit is configured in software and hardware enabled by the wp# pin. note that the s3/s5s command code to lock blocks is different from the sa/sv. see the datasheets for the write protection alternatives available on the s3/s5. within the s3/s5, a block lock-bit is assigned to each block. with wp# high, this block lock-bit can be set in software with the set block lock-bit command (60h/01h). this is a two-step sequence which ensures that block lock-bits are not accidentally set. when wp# is low, all blocks with their block lock-bit set are locked. locked blocks cannot be programmed, erased, or have their block lock-bit configured. attempting to perform these operations on a locked block will result in status register bits sr.4 and sr.5 being set to 1, indicating an improper command sequence. a full chip erase command (30h/d0h) with wp# active will erase only those blocks which are not locked. the clear block lock-bits command (60h/d0h) simultaneously clears all of the block lock-bits. this is also a two-step sequence to protect against accidental clearing of block lock-bits. similarly, this command will only clear the lock-bits when wp# is high. the status of the block lock-bit can be found in one of two ways. the read identifier codes command can be used to access the block lock configuration codes (see section 4.4.2). alternatively, the read query command can be used to access the block status register (see section 4.4.1). 4.4.5 writing to the buffer the architecture of the s3/s5 incorporates two 32-byte write buffers. this reduction in capacity from the 256- byte buffers found in the sa/sv lowers the cost of the s3/s5 without sacrificing performance. using the write to buffer command (e8h) allows for writes at 2.0 m s/byte effective on the 28f160/320s5, and 2.7 m s/byte effective on the 28f160/320s3. the functionality of the page buffers is similar between the sa/sv and s3/s5, but the commands used to operate the page buffers differ. the sa/svs single load to page buffer, sequential load to page buffer and page buffer write to flash commands have all been replaced by the write to buffer and confirm commands on the s3/s5. 4.4.6 full chip erase the s3/s5 incorporates a full chip erase command (30h/d0h) which replaces the erase all unlocked blocks command on the sa/sv. the full chip erase command, followed by a confirm command, will erase all unlocked blocks when wp# is low, and will erase the entire chip when wp# is high. the full chip erase command can be suspended to read from locked blocks when wp# is low. 4.4.7 sts configuration the sts pin on the s3/s5 can be configured to four different pulse modes. this capability is similar to the sa/svs ry/by# pin configuration. table 8 shows each parts configuration options. the s3/s5s sts pin is configured using a two bus cycle command set, including the sts configuration command (b8h) and the configuration code (cc). refer to the s3/s5 datasheets for the configuration coding definitions. 4.4.8 commands not supported on the s3/s5 the read extended status registers (xsrs), read page buffer, page buffer swap, two-byte program, upload status bits, upload device information, sleep, and abort commands are not directly replaced in the s3/s5s scaleable command set. some commands are now performed automatically by the device, and others are not used.
ap-645 e 12 the status register structure is different between the sa/sv and s3/s5. because of this change, some commands are no longer used on the s3/s5. the read extended status registers command (71h) has been deleted. however, an extended status register (xsr) and block status register (bsr) do exist. the xsr is automatically polled by the s3/s5 when a write to buffer command is issued. the bsr can be read from address 02h within each block by using the read query command. in addition, the upload status bits command (97h), which was used to update status in the sa/svs bsr and gsr, is no longer necessary. see section 4.6 for more information on status registers. the read page buffer (75h) and page buffer swap (72h) commands are not available on the s3/s5. the page buffer cannot be read on the s3/s5, and there is no manual page buffer swap. the sa/svs single load to page buffer, sequential load to page buffer and page buffer write to flash commands have all been replaced by the write to buffer and confirm commands on the s3/s5. in addition, the upload device information command (99h) on the sa/sv wrote information into the page buffers including the device revision number (28f016sa and 28f016sv), device proliferation code (28f016sv only), and device configuration code (28f016sv only). this command is not available on the s3/s5, however, similar types of information can be found in the query database. see section 4.4.1 and the datasheets for more information on the query database. the two-byte program command (fbh) is not available on the s3/s5. the abort command (80h) does not exist on the s3/s5. a write to buffer command can be aborted by issuing an address outside of the current block address. other operations can be aborted by bringing rp# low. the sleep command (f0h) is not supported on the s3/s5. the device does not have a sleep mode like the sa/sv. 4.5 command queuing there is no command queuing on the s3/s5. however, cfi supports command queuing, and the block erase flowchart in the s3/s5 datasheet contains the steps necessary to incorporate command queuing on future devices. applications which use command queuing on the sa/sv will have to use software to account for the lack of command queuing on the s3/s5. software which previously took advantage of the command queuing capability of the sa/sv can be updated by polling for sr.7 = 1 (wsm ready) before issuing any new commands to the command user interface (cui). an alternative is to create new software which does not incorporate command queuing. 4.6 status registers the sa/sv devices have a compatible status register (csr), global status register (gsr) and 32 block status registers (bsrs). most of the information reflected in these three status registers has been compressed into a single status register (sr) on the s3/s5. the 28f160/320, s3/s5 status register has the same structure as the 28f008/016, s3/s5 status register. the s3/s5 has two additional status registers: the block status register (bsr) and the extended status register (xsr). the s3/s5s bsr, unlike the sa/svs bsr, is included in the cfi information and can be accessed by using the read query command. the s3/s5s xsr is accessed when a write to buffer command is issued. devices which incorporate cfi erase queuing access the xsr during queued erase operations. the device accesses the xsr automatically in both cases. table 8. sts and ry/by# configurations configuration s3/s5 (sts) 28f016sa (ry/by#) 28f016sv (ry/by#) level mode ry/by# (default mode) 44 4 pulse on erase complete 44 4 pulse on program complete 44 4 pulse on erase or program complete 44 disable 44
e ap-645 13 the status register on the s3/s5 can be read at any time by issuing a read status register command (70h). status register data is also available to be read after the completion of a program, block erase, set lock-bit or clear lock-bits command sequence. bits which are masked in the sa/sv csr should not be masked when reading the s3/s5 status register. for the full s3/s5 status register descriptions, see the s3/s5 datasheets. table 9 gives a cross-reference for the various status register bits from the sa/sv to the s3/s5. 5.0 design for forward- compatibility manufacturers that use the sa/sv and plan to move to the s3/s5 in the future for cost reduction, cfi-scs compliance, or other reasons should keep these design considerations in mind. 5.1 hardware 5.1.1 pinout to create a footprint which can accommodate both a sa/sv and s3/s5 pinout, the following procedures should be followed: 1. connect the sa/svs 3/5# pin to the correct level for its operation. this voltage level does not have to change when converting to the s3/s5 since the pin becomes a no connect. 2. the sts and ry/by# pins have the same function in hardware. however, the sts pin cannot be disabled like the ry/by# pin. as long as these two pins are configured to the same mode in software, there are no hardware changes required. 3. connect the a 21 pin when using a 28f320s3/s5 device. pinout changes are discussed in section 3.1. refer to sections 5.1.2 and 5.1.3 for information on v cc and v pp .
ap-645 e 14 table 9. status register bit cross reference: sa/sv to s3/s5 status s3/s5 sa/sv csr sa/sv gsr sa/sv bsr notes write state machine status sr.7 csr.7 gsr.7 erase-suspend status sr.6 csr.6 program-suspend status sr.2 n/a 1 operation suspend status sr.6 or sr.2 gsr.6 1 erase status sr.5 csr.5 2 data-write status sr.4 csr.4 2 device operation status sr.5 or sr.4 gsr.5 2 improper command sequence sr.5 and sr.4 csr.5 and csr.4 device sleep status n/a gsr.4 3 block status sr.1 bsr.7 5 block lock status bsr.0 bsr.6 4 block operation status bsr.1, sr.5 or sr.4 bsr.5 4,5 block operation abort status n/a bsr.4 6 queue status n/a (xsr.7) gsr.3 bsr.3 7 v pp status sr.3 csr.3 bsr.2 v pp level (28f016sv only) n/a bsr.1 6 page buffer available status xsr.7 gsr.2 page buffer status n/a gsr.1 6 page buffer select status n/a gsr.0 6 reserved xsr.0 C6 bsr.2C7 sr.0 csr.2C0 bsr.0 notes: 1. the s3/s5s sr.6 gives erase suspend information and sr.2 gives program suspend information. 2. the s3/s5s sr.4 and sr.5 also give set block lock-bit status and clear lock-bits status, respectively. 3. the s3/s5 does not have a sleep mode. 4. the s3/s5s bsr.0 and bsr.1 can be read using the read query command. see section 4.4.7. 5. the s3/s5s sr.1, sr.5 and sr.4 give overall device information and are not block specific. 6. there are no status register bits in the s3/s5 which reflect this information. 7. the s3/s5 does not support command queuing. cfi-scs compliant software that supports command queuing should poll xsr.7 for queue status.
e ap-645 15 5.1.2 v cc voltage v cc voltage options differ slightly between the devices (refer to table 10). table 10. v cc voltage comparison 28f160 28f320 v cc voltage 16sa 16sv s3 s5 5.0 v 44 4 3.3 v 444 2.7 v 4 one migration path between the sa/sv and the s3/s5 is to use the same v cc value on both devices. the sa/sv and 28f160s5 are capable of using 5 v v cc . the sa/sv and 28f160s3 are capable of using 3.3 v v cc . however, it should be noted there are some ac characteristic differences between the parts at the same v cc values (see the datasheets for further information). applications that wish to take advantage of the 2.7 v v cc operation of the s3/s5 can implement a jumper, as shown in figure 2 the v cc(original) (3.3 0.3 v) can be supplied from a converter and later removed after the conversion to s3/s5 has taken place v cc (new) (2.7 v-3.6 v) power supply v cc (original) (3.0 v-3.6 v) converter v cc (new) v cc (original) jp1 v cc flash memory 2203_02 figure 2. v cc jumper selection the s3/s5s v cc maximum standby current is less than the 28f016sv and the same as the 28f016sa. however, for the v cc read current, the current values are tested at separate frequencies between the three devices. refer to the datasheets for dc specification differences. conversion of sa/sv to the s3/s5 will most likely involve v pp conversion from 12 v or 5 v to 2.7 v, 3.3 v, or 5 v. because of this conversion, power supply current calculations should take into account the initial v cc value, as well as an additional v pp connection that may be present upon conversion. 5.1.3 v pp voltage v pp voltage options differ between the devices. table 11 shows a v pp voltage comparison. it is possible to get the same or better write timings on the 28f160/320s5 at 5 v v pp as on the 28f016sv at 12 v v pp . table 11. v pp voltage comparison 28f160 28f320 v pp voltage 16sa 16sv s3 s5 12.0 v 44 5.0 v 444 3.3 v 4 2.7 v 4 to design in a 28f016sa today for migration to a s3/s5 in the future, it will be necessary to provide a jumper from 12 v v pp to 2.7 v, 3.3 v, or 5 v v pp as shown in figure 3. in this case, v pp (original) is 12 v, supplied from a converter. v pp(new) will be 2.7 v, 3.3 v, or 5 v. once conversion has taken place, the 12 v converter can be removed. dc and ac characteristic differences should be taken into account as well (refer to the datasheets). to design in a 28f016sv for migration to the s3/s5 in the future, 5 v v pp can be used for both devices. there are some dc specifications that differ in this case (refer to the datasheets). some ac write timings differ between the devices (refer to the datasheets). designs requiring fast programming should use 12 v v pp on the 28f016sv and later convert to 5 v v pp on the s3/s5. a jumper, such as the one shown in figure 3, can be used. designs requiring low power may want to use 2.7 v or 3.3 v v pp after conversion to the 28f160/320s3. this operation can be accomplished by a jumper as well. v pp (original) (12 v) converter v pp (new) (2.7 v, 3.3 v, or 5.0 v) power supply v pp (original) v pp (new) jp2 v pp flash memory 2203_03 figure 3. v pp jumper selection
ap-645 e 16 5.1.4 write protection via v pplk switching v pp off when not in use is a common write protection technique. it is necessary to switch v pp below v pplk to ensure write protection on the 28f016sv and s3/s5. see section 3.3 for further information. 5.1.5 read/write performance conversion to the s3/s5 may also be driven by its higher write performance. component identification to determine whether the 28f016sa, 28f016sv or s3/s5 is in system can be accomplished via software methods (see section 5.2.2). depending on which component resides in the system, the state machine within the interface logic and/or system software can modify the program time of the flash memory space to take advantage of the s3/s5s higher write performance capability. 5.2 software 5.2.1 command set compatibility applications using only the intel basic command set (bcs) can use the same software for the sa/sv and the s3/s5. applications using the sa/sv performance- enhancement commands should create one branch of software for the sa/sv and one branch of software for the s3/s5. identifying whether the 28f016sa, 28f016sv or s3/s5 is in a system can be accomplished via software methods (see section 5.2.2). 5.2.2 software identification of 28f016sa, 28f016sv or 28f160s3/s5 the s3/s5 can be identified using the read query command (98h). after sending this command, a return of the ascii qry will indicate the presence of a cfi- compliant device. if a cfi-compliant device is found, reading of the cfi database will allow software to identify the device as the s3/s5 or another cfi- compliant device. if the qry data is not found, the read identifiers code command (90h) should be issued to the device to read the intelligent identifier codes of the sa/sv. for more information, refer to ap-646 , common flash interface and command sets . 6.0 conclusion this application note has summarized migration and compatibility considerations between the sa/sv and the s3/s5. the major differences that need to be considered for migrations are: three pinout differences input voltage differences ac and dc specification differences software differences refer to the documentation listed in appendix a for more information on compatibility and device capabilities. please contact your local intel sales office, distribution sales office, or visit intels world wide web home page at http://www.intel.com for add itional technical documentation and tools.
e ap-645 17 appendix a additional information order number document/tool 290609 5 volt flashfile tm memory; 28f160s5 and 28f320s5 datasheet 290608 3 volt flashfile tm memory; family 28f160s3 and 28f320s3 datasheet 292204 ap-646 common flash interface and command sets 292163 ap-610 flash memory in-system code and data update techniques 292144 ap-393 28f016sv compatibility with 28f016sa 292124 ap-375 upgrade considerations from the 28f008sa to the 28f016sa 292123 ap-374 flash memory write protection techniques 292092 ap-357 power supply solutions for flash memory note 3 28f016sv 16-mbit (1 mbit x 16, 2 mbit x 8) flashfile? memory datasheet note 3 28f016sa 16-mbit (1 mbit x 16, 2 mbit x 8) flashfile? memory datasheet www.mcif.org common flash interface specification contact intel/distribution sales office cfi - common flash interface reference code notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools. 3. these documents can be located at the intel world wide web support site, http://www.intel.com/support/flash/memory

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